1. Technical Field
The present invention relates generally to semiconductor processing, and more particularly to a method for enhancing etch selectivity for a tunable etch resistant anti-reflective (TERA) layer and a method of generating a nanostructure and a nanostructure such as a gate stack.
2. Related Art
Microelectronic devices are continually made smaller-and-smaller. To fabricate ever smaller devices, new lithographic tools, materials and processes are being considered. Currently, 193 nm lithography is being pursued to print sub-110 nm features. To do this, tools with higher numerical aperture (NA) are emerging. The higher NA allows for improved resolution but reduces the depth of focus of aerial images projected onto the photoresist. Because of the reduced depth of focus, a thinner photoresist is required.
Typical photoresist structures consist of a photoresist layer on top of an antireflective coating (ARC). The photoresist is exposed and developed and the image is then transferred through the ARC and then through the underlying silicon dioxide (hereinafter “oxide”), silicon nitride (hereinafter “nitride”) or silicon layers. Typical photoresist thickness is on the order of 2000–2500 A for the current state-of-the-art lithography process. During the ARC open, significant resist is lost as the etch selectivity between the photoresist and ARC is at best 1:1. “Etch selectivity” is a ratio of an amount of an etch-target material etched away versus an amount of photoresist etched away in a single etching step.
As minimum feature size continues to decrease, it is desirable to thin the photoresist to attain the high resolution as well as improve process window exposure and focus latitude. Unfortunately, as the thickness of the photoresist is decreased, the photoresist becomes less effective as a mask for subsequent dry etch image transfer to the underlying substrate, i.e., most if not all of the resist is etched away during the subsequent pattern transfer process. In other words, there will be insufficient photoresist to function as an etch mask for subsequent transfer etch into the oxide, nitride or silicon layer. Compounding this problem is the fact that significant photoresist loss also occurs during the ARC open.
In a typical dielectric mask open etch, there are two types of etching steps as follows: Etching type I including pattern transfer through an ARC with etch selectivity to the patterned photoresist, and etching type II including pattern transfer through a dielectric layer (i.e., open mask) requiring etch selectivity to the remaining resist/ARC layer. For current generation (193 nm) device fabrication and for etching type I, etch selectivity for photoresists and ARCs varies from 0.5 to 1.5. In contrast, for etching type II, etch selectivity ranges from 1 to 10 where, for example, the dielectric is thermal oxide or TEOS or high temperature oxide (HTO). However, for etching type II where the dielectric is nitride, current etch selectivity's are very limited, typically about 1–2.
This situation presents a challenge for the next device generation (65 nm) and beyond because integration schemes for this generation of devices are likely to require patterning of nitride layers for the poly/metal conductor/gate (PC) level. Techniques for patterning the PC level of the current generation and beyond with, for example, less than 200 nm of photoresist thickness via mask open shall require higher etch selectivity for etching type II of nitride than currently available.
Reduced photoresist thickness also creates other problems. First, reduced photoresist thickness tends to increase line edge roughness (LER) of the photoresist. The LER of the imaged photoresist and the pattern transfer through dielectric mask open can contribute to overall critical dimension (CD) variation of lines. Second, reduced photoresist thickness hinders the ability to trim. “Trimming” is a common method for reducing the linewidth of the polysilicon/metal gate level (for speedier device performance), which employs a dry etch process during pattern transfer of the photolithographic pattern in which the organic ARC is both opened (cleared to the bottom of the arc) and reduced in width (along with the remaining resist). This process typically has a vertical to lateral component of 3:1. Accordingly, the amount of trim available is limited by resist thickness. Current techniques for patterning PC level for the 65 nm generation of devices and beyond, with less then 200 nm of photoresist thickness, severely restricts the ability to trim, which is critical to device performance.
One possible approach to address reduced photoresist thickness is to implement a complex set of sequential etching steps through an ARC, and intermediate hard mask such as oxide (e.g., TEOS) and silicon nitride layers, using current integration methodology. However, satisfactory implementation of this approach is very difficult to achieve.
Concurrent to the emergence of the above photoresist thickness reduction problem, a new ARC material has been developed as disclosed in U.S. Pat. Nos. 6,26,167 and 6,514,667, both to Angelopoulus et al., which are hereby incorporated by reference. In these disclosures, a photoresist is provided on top of a plasma-enhanced chemical vapor deposited (PECVC) ARC. The ARC provides significantly better etch selectivity to the photoresist (>1:1) and does not interact with the photoresist in a negative fashion inducing footing, undercutting or residue as is characteristic of silicon oxy nitride ARC. The improved ARC material may have composition R:C:H:X wherein R is selected from Si, Ge, B, Sn, Fe, Ti and mixtures of these elements and X is selected from O, N, S, F and mixtures of these elements and X is optionally present. The optical properties of the vapor deposited ARC can be tuned by variations in the deposition process. Furthermore, the optical properties can also be tuned within the film thickness thereby forming a graded ARC. The vapor deposited ARC also functions as a hardmask or as a combined ARC-hardmask. In view of the foregoeing, the structure is referred to herein as a tunable etch-resistant anti-reflective (TERA) material. Unfortunately, while the TERA material provides excellent optical properties as an ARC, when used as hardmask, it provides good etch selectivity for etching type I (approximately 1.5 to 2.5), but inadequate etch selectivity etching type II of nitride (approximately 2).
In view of the foregoing, there is a need in the art for a methods and materials that address the problems of the related art.